Farmer Lab Overview
One of the lab classes I taught as a TA at SCU was Advanced Logic Design. I had the opportunity to create my own lab from scratch. The students were learning about state machines in the lecture at the time so I decided to have a state machine based lab. I remembered reading about a puzzle problem from an undergraduate operating system class I had taken several years ago called "The Farmer, Fox, Chicken and Seeds". I wanted to recreate that puzzle and have the students implement it on an FPGA. Below is the lab handout I created and the Verilog solution for the problem. The lab was implemented on a Terasic DE2-115 FPGA board using Altera's Quartus II software.