// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================

`timescale 1 ns / 1 ps

module doDecode_decode (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        indat_V,
        ap_return
);

parameter    ap_ST_pp0_stg0_fsm_0 = 1'b1;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv4_0 = 4'b0000;
parameter    ap_const_lv4_2 = 4'b10;
parameter    ap_const_lv2_3 = 2'b11;
parameter    ap_const_lv4_1 = 4'b1;
parameter    ap_const_lv2_2 = 2'b10;
parameter    ap_const_lv2_1 = 2'b1;
parameter    ap_const_lv2_0 = 2'b00;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv4_4 = 4'b100;
parameter    ap_const_lv4_8 = 4'b1000;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [1:0] indat_V;
output  [0:0] ap_return;

reg ap_done;
reg ap_idle;
reg ap_ready;

(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
reg    ap_sig_cseq_ST_pp0_stg0_fsm_0;
reg    ap_sig_18;
wire    ap_reg_ppiten_pp0_it0;
reg    ap_reg_ppiten_pp0_it1;
reg    ap_reg_ppiten_pp0_it2;
reg    ap_reg_ppiten_pp0_it3;
reg    ap_reg_ppiten_pp0_it4;
reg    ap_reg_ppiten_pp0_it5;
reg    ap_reg_ppiten_pp0_it6;
reg    ap_reg_ppiten_pp0_it7;
reg    ap_reg_ppiten_pp0_it8;
reg    ap_reg_ppiten_pp0_it9;
reg    ap_reg_ppiten_pp0_it10;
reg    ap_reg_ppiten_pp0_it11;
reg    ap_reg_ppiten_pp0_it12;
reg    ap_reg_ppiten_pp0_it13;
reg    ap_reg_ppiten_pp0_it14;
reg    ap_reg_ppiten_pp0_it15;
reg    ap_reg_ppiten_pp0_it16;
reg    ap_reg_ppiten_pp0_it17;
reg   [3:0] viterbiDecoder_distance_V_0;
reg   [3:0] viterbiDecoder_distance_V_1;
reg   [3:0] viterbiDecoder_distance_V_2;
reg   [3:0] viterbiDecoder_distance_V_3;
reg   [3:0] viterbiDecoder_globalDistance_3;
reg   [3:0] viterbiDecoder_globalDistance_1;
reg   [3:0] viterbiDecoder_survivors_V;
reg   [3:0] viterbiDecoder_globalDistance_2;
reg   [3:0] viterbiDecoder_globalDistance_s;
reg   [3:0] viterbiDecoder_survivorWindow_14;
reg   [3:0] viterbiDecoder_survivorWindow_7;
reg   [3:0] viterbiDecoder_survivorWindow_6;
reg   [3:0] viterbiDecoder_survivorWindow_5;
reg   [3:0] viterbiDecoder_survivorWindow_4;
reg   [3:0] viterbiDecoder_survivorWindow_3;
reg   [3:0] viterbiDecoder_survivorWindow_2;
reg   [3:0] viterbiDecoder_survivorWindow_1;
reg   [3:0] viterbiDecoder_survivorWindow_s;
reg   [3:0] viterbiDecoder_survivorWindow_13;
reg   [3:0] viterbiDecoder_survivorWindow_12;
reg   [3:0] viterbiDecoder_survivorWindow_11;
reg   [3:0] viterbiDecoder_survivorWindow_10;
reg   [3:0] viterbiDecoder_survivorWindow_9;
reg   [3:0] viterbiDecoder_survivorWindow_8;
wire   [1:0] indat_V_read_read_fu_90_p2;
wire   [0:0] tmp_s_fu_212_p2;
reg   [0:0] tmp_s_reg_1857;
wire   [0:0] tmp_27_1_fu_238_p2;
reg   [0:0] tmp_27_1_reg_1862;
wire   [0:0] tmp_27_2_fu_296_p2;
reg   [0:0] tmp_27_2_reg_1867;
wire   [0:0] tmp_27_3_fu_322_p2;
reg   [0:0] tmp_27_3_reg_1872;
wire   [0:0] tmp_9_fu_336_p2;
reg   [0:0] tmp_9_reg_1877;
wire   [0:0] tmp_25_1_fu_350_p2;
reg   [0:0] tmp_25_1_reg_1882;
wire   [0:0] tmp_25_2_fu_364_p2;
reg   [0:0] tmp_25_2_reg_1887;
reg   [0:0] ap_reg_ppstg_tmp_25_2_reg_1887_pp0_iter2;
wire   [3:0] viterbiDecoder_survivorWindow_15_fu_567_p3;
reg   [3:0] viterbiDecoder_survivorWindow_15_reg_1894;
reg   [3:0] ap_reg_ppstg_viterbiDecoder_survivorWindow_15_reg_1894_pp0_iter3;
wire   [1:0] p_viterbiDecoder_state_V_load_s_fu_594_p3;
reg   [1:0] p_viterbiDecoder_state_V_load_s_reg_1899;
wire   [0:0] tmp_20_fu_606_p3;
reg   [0:0] tmp_20_reg_1907;
wire   [1:0] viterbiDecoder_state_V_load_1_fu_661_p3;
reg   [1:0] viterbiDecoder_state_V_load_1_reg_1913;
reg   [3:0] viterbiDecoder_survivorWindow_s_reg_1923;
wire   [1:0] viterbiDecoder_state_V_load_2_fu_739_p3;
reg   [1:0] viterbiDecoder_state_V_load_2_reg_1928;
reg   [3:0] viterbiDecoder_survivorWindow_1_reg_1938;
wire   [1:0] viterbiDecoder_state_V_load_3_fu_822_p3;
reg   [1:0] viterbiDecoder_state_V_load_3_reg_1943;
reg   [3:0] viterbiDecoder_survivorWindow_2_reg_1953;
wire   [1:0] viterbiDecoder_state_V_load_4_fu_905_p3;
reg   [1:0] viterbiDecoder_state_V_load_4_reg_1958;
reg   [3:0] viterbiDecoder_survivorWindow_3_reg_1968;
wire   [1:0] viterbiDecoder_state_V_load_5_fu_988_p3;
reg   [1:0] viterbiDecoder_state_V_load_5_reg_1973;
reg   [3:0] viterbiDecoder_survivorWindow_4_reg_1983;
wire   [1:0] viterbiDecoder_state_V_load_6_fu_1071_p3;
reg   [1:0] viterbiDecoder_state_V_load_6_reg_1988;
reg   [3:0] viterbiDecoder_survivorWindow_5_reg_1998;
wire   [1:0] viterbiDecoder_state_V_load_7_fu_1154_p3;
reg   [1:0] viterbiDecoder_state_V_load_7_reg_2003;
reg   [3:0] viterbiDecoder_survivorWindow_6_reg_2013;
wire   [1:0] viterbiDecoder_state_V_load_8_fu_1237_p3;
reg   [1:0] viterbiDecoder_state_V_load_8_reg_2018;
reg   [3:0] viterbiDecoder_survivorWindow_7_reg_2028;
wire   [1:0] viterbiDecoder_state_V_load_9_fu_1320_p3;
reg   [1:0] viterbiDecoder_state_V_load_9_reg_2033;
reg   [3:0] viterbiDecoder_survivorWindow_8_reg_2043;
wire   [1:0] viterbiDecoder_state_V_load_10_fu_1403_p3;
reg   [1:0] viterbiDecoder_state_V_load_10_reg_2048;
reg   [3:0] viterbiDecoder_survivorWindow_9_reg_2058;
wire   [1:0] viterbiDecoder_state_V_load_11_fu_1486_p3;
reg   [1:0] viterbiDecoder_state_V_load_11_reg_2063;
reg   [3:0] viterbiDecoder_survivorWindow_10_reg_2073;
wire   [1:0] viterbiDecoder_state_V_load_12_fu_1569_p3;
reg   [1:0] viterbiDecoder_state_V_load_12_reg_2078;
reg   [3:0] viterbiDecoder_survivorWindow_11_reg_2088;
wire   [1:0] viterbiDecoder_state_V_load_13_fu_1652_p3;
reg   [1:0] viterbiDecoder_state_V_load_13_reg_2093;
reg   [3:0] viterbiDecoder_survivorWindow_12_reg_2103;
wire   [1:0] viterbiDecoder_state_V_load_14_fu_1735_p3;
reg   [1:0] viterbiDecoder_state_V_load_14_reg_2108;
wire   [3:0] r_V_fu_386_p2;
wire   [3:0] r_V_2_fu_418_p2;
wire   [3:0] r_V_1_fu_402_p2;
wire   [3:0] r_V_3_fu_434_p2;
wire   [2:0] tmp_2_fu_180_p1;
wire   [2:0] tmp_1_fu_172_p1;
wire   [2:0] tmp_5_fu_202_p1;
wire   [2:0] tmp_4_fu_194_p1;
wire   [2:0] tmp_3_fu_184_p2;
wire   [2:0] tmp_6_fu_206_p2;
wire   [2:0] tmp_9_1_fu_226_p2;
wire   [2:0] tmp_11_1_fu_232_p2;
wire   [2:0] tmp_13_fu_256_p1;
wire   [2:0] tmp_14_fu_264_p1;
wire   [2:0] tmp_15_fu_278_p1;
wire   [2:0] tmp_16_fu_286_p1;
wire   [2:0] tmp_14_2_fu_268_p2;
wire   [2:0] tmp_17_2_fu_290_p2;
wire   [2:0] tmp_20_3_fu_310_p2;
wire   [2:0] tmp_23_3_fu_316_p2;
wire   [2:0] viterbiDecoder_branchDistance_1_fu_244_p3;
wire   [2:0] viterbiDecoder_branchDistance_s_fu_218_p3;
wire   [2:0] viterbiDecoder_branchDistance_2_fu_302_p3;
wire   [2:0] sel_SEBB_fu_342_p3;
wire   [2:0] viterbiDecoder_branchDistance_3_fu_328_p3;
wire   [2:0] viterbiDecoder_minimumBranch_V_fu_356_p3;
wire   [2:0] sel_SEBB1_fu_370_p3;
wire   [3:0] lhs_V_fu_378_p1;
wire   [3:0] rhs_V_fu_382_p1;
wire   [3:0] lhs_V_1_fu_398_p1;
wire   [3:0] lhs_V_2_fu_414_p1;
wire   [3:0] lhs_V_3_fu_430_p1;
wire   [2:0] tmp_10_fu_450_p4;
wire   [3:0] tmp_8_fu_468_p2;
wire   [3:0] tmp_7_fu_460_p3;
wire   [3:0] viterbiDecoder_survivors_V_loa_1_fu_474_p3;
wire   [1:0] tmp_11_fu_481_p4;
wire   [0:0] tmp_12_fu_491_p1;
wire   [3:0] tmp_30_1_fu_505_p2;
wire   [3:0] tmp_34_1_fu_495_p4;
wire   [3:0] viterbiDecoder_survivors_V_loa_2_fu_511_p3;
wire   [0:0] tmp_17_fu_518_p3;
wire   [1:0] tmp_18_fu_526_p1;
wire   [3:0] tmp_30_2_fu_540_p2;
wire   [3:0] tmp_34_2_fu_530_p4;
wire   [3:0] viterbiDecoder_survivors_V_loa_3_fu_546_p3;
wire   [2:0] tmp_19_fu_553_p1;
wire   [3:0] tmp_30_3_fu_561_p2;
wire   [3:0] tmp_34_3_cast_fu_557_p1;
wire   [0:0] tmp_fu_590_p2;
wire   [1:0] viterbiDecoder_state_V_load_s_fu_583_p3;
wire   [1:0] p_s_fu_580_p1;
wire   [31:0] index_assign_fu_602_p1;
wire   [0:0] sel_tmp_fu_628_p2;
wire   [0:0] sel_tmp2_fu_633_p2;
wire   [1:0] storemerge2_fu_621_p3;
wire   [0:0] sel_tmp4_fu_645_p2;
wire   [0:0] sel_tmp5_fu_650_p2;
wire   [0:0] sel_tmp6_fu_655_p2;
wire   [1:0] storemerge1_fu_614_p3;
wire   [1:0] sel_tmp3_fu_638_p3;
wire   [31:0] index_assign_1_fu_673_p1;
wire   [0:0] tmp_21_fu_676_p3;
wire   [0:0] sel_tmp8_fu_700_p2;
wire   [0:0] sel_tmp9_fu_705_p2;
wire   [0:0] sel_tmp1_fu_710_p2;
wire   [1:0] storemerge2_1_fu_692_p3;
wire   [0:0] sel_tmp10_fu_723_p2;
wire   [0:0] sel_tmp11_fu_728_p2;
wire   [0:0] sel_tmp12_fu_733_p2;
wire   [1:0] storemerge1_1_fu_684_p3;
wire   [1:0] sel_tmp7_fu_716_p3;
wire   [31:0] index_assign_2_fu_756_p1;
wire   [0:0] tmp_22_fu_759_p3;
wire   [0:0] sel_tmp13_fu_783_p2;
wire   [0:0] sel_tmp14_fu_788_p2;
wire   [0:0] sel_tmp15_fu_793_p2;
wire   [1:0] storemerge2_2_fu_775_p3;
wire   [0:0] sel_tmp17_fu_806_p2;
wire   [0:0] sel_tmp18_fu_811_p2;
wire   [0:0] sel_tmp19_fu_816_p2;
wire   [1:0] storemerge1_2_fu_767_p3;
wire   [1:0] sel_tmp16_fu_799_p3;
wire   [31:0] index_assign_3_fu_839_p1;
wire   [0:0] tmp_23_fu_842_p3;
wire   [0:0] sel_tmp20_fu_866_p2;
wire   [0:0] sel_tmp21_fu_871_p2;
wire   [0:0] sel_tmp22_fu_876_p2;
wire   [1:0] storemerge2_3_fu_858_p3;
wire   [0:0] sel_tmp24_fu_889_p2;
wire   [0:0] sel_tmp25_fu_894_p2;
wire   [0:0] sel_tmp26_fu_899_p2;
wire   [1:0] storemerge1_3_fu_850_p3;
wire   [1:0] sel_tmp23_fu_882_p3;
wire   [31:0] index_assign_4_fu_922_p1;
wire   [0:0] tmp_24_fu_925_p3;
wire   [0:0] sel_tmp27_fu_949_p2;
wire   [0:0] sel_tmp28_fu_954_p2;
wire   [0:0] sel_tmp29_fu_959_p2;
wire   [1:0] storemerge2_4_fu_941_p3;
wire   [0:0] sel_tmp31_fu_972_p2;
wire   [0:0] sel_tmp32_fu_977_p2;
wire   [0:0] sel_tmp33_fu_982_p2;
wire   [1:0] storemerge1_4_fu_933_p3;
wire   [1:0] sel_tmp30_fu_965_p3;
wire   [31:0] index_assign_5_fu_1005_p1;
wire   [0:0] tmp_25_fu_1008_p3;
wire   [0:0] sel_tmp34_fu_1032_p2;
wire   [0:0] sel_tmp35_fu_1037_p2;
wire   [0:0] sel_tmp36_fu_1042_p2;
wire   [1:0] storemerge2_5_fu_1024_p3;
wire   [0:0] sel_tmp38_fu_1055_p2;
wire   [0:0] sel_tmp39_fu_1060_p2;
wire   [0:0] sel_tmp40_fu_1065_p2;
wire   [1:0] storemerge1_5_fu_1016_p3;
wire   [1:0] sel_tmp37_fu_1048_p3;
wire   [31:0] index_assign_6_fu_1088_p1;
wire   [0:0] tmp_26_fu_1091_p3;
wire   [0:0] sel_tmp41_fu_1115_p2;
wire   [0:0] sel_tmp42_fu_1120_p2;
wire   [0:0] sel_tmp43_fu_1125_p2;
wire   [1:0] storemerge2_6_fu_1107_p3;
wire   [0:0] sel_tmp45_fu_1138_p2;
wire   [0:0] sel_tmp46_fu_1143_p2;
wire   [0:0] sel_tmp47_fu_1148_p2;
wire   [1:0] storemerge1_6_fu_1099_p3;
wire   [1:0] sel_tmp44_fu_1131_p3;
wire   [31:0] index_assign_7_fu_1171_p1;
wire   [0:0] tmp_27_fu_1174_p3;
wire   [0:0] sel_tmp48_fu_1198_p2;
wire   [0:0] sel_tmp49_fu_1203_p2;
wire   [0:0] sel_tmp50_fu_1208_p2;
wire   [1:0] storemerge2_7_fu_1190_p3;
wire   [0:0] sel_tmp52_fu_1221_p2;
wire   [0:0] sel_tmp53_fu_1226_p2;
wire   [0:0] sel_tmp54_fu_1231_p2;
wire   [1:0] storemerge1_7_fu_1182_p3;
wire   [1:0] sel_tmp51_fu_1214_p3;
wire   [31:0] index_assign_8_fu_1254_p1;
wire   [0:0] tmp_28_fu_1257_p3;
wire   [0:0] sel_tmp55_fu_1281_p2;
wire   [0:0] sel_tmp56_fu_1286_p2;
wire   [0:0] sel_tmp57_fu_1291_p2;
wire   [1:0] storemerge2_8_fu_1273_p3;
wire   [0:0] sel_tmp59_fu_1304_p2;
wire   [0:0] sel_tmp60_fu_1309_p2;
wire   [0:0] sel_tmp61_fu_1314_p2;
wire   [1:0] storemerge1_8_fu_1265_p3;
wire   [1:0] sel_tmp58_fu_1297_p3;
wire   [31:0] index_assign_9_fu_1337_p1;
wire   [0:0] tmp_29_fu_1340_p3;
wire   [0:0] sel_tmp62_fu_1364_p2;
wire   [0:0] sel_tmp63_fu_1369_p2;
wire   [0:0] sel_tmp64_fu_1374_p2;
wire   [1:0] storemerge2_9_fu_1356_p3;
wire   [0:0] sel_tmp66_fu_1387_p2;
wire   [0:0] sel_tmp67_fu_1392_p2;
wire   [0:0] sel_tmp68_fu_1397_p2;
wire   [1:0] storemerge1_9_fu_1348_p3;
wire   [1:0] sel_tmp65_fu_1380_p3;
wire   [31:0] index_assign_s_fu_1420_p1;
wire   [0:0] tmp_30_fu_1423_p3;
wire   [0:0] sel_tmp69_fu_1447_p2;
wire   [0:0] sel_tmp70_fu_1452_p2;
wire   [0:0] sel_tmp71_fu_1457_p2;
wire   [1:0] storemerge2_s_fu_1439_p3;
wire   [0:0] sel_tmp73_fu_1470_p2;
wire   [0:0] sel_tmp74_fu_1475_p2;
wire   [0:0] sel_tmp75_fu_1480_p2;
wire   [1:0] storemerge1_s_fu_1431_p3;
wire   [1:0] sel_tmp72_fu_1463_p3;
wire   [31:0] index_assign_10_fu_1503_p1;
wire   [0:0] tmp_31_fu_1506_p3;
wire   [0:0] sel_tmp76_fu_1530_p2;
wire   [0:0] sel_tmp77_fu_1535_p2;
wire   [0:0] sel_tmp78_fu_1540_p2;
wire   [1:0] storemerge2_10_fu_1522_p3;
wire   [0:0] sel_tmp80_fu_1553_p2;
wire   [0:0] sel_tmp81_fu_1558_p2;
wire   [0:0] sel_tmp82_fu_1563_p2;
wire   [1:0] storemerge1_10_fu_1514_p3;
wire   [1:0] sel_tmp79_fu_1546_p3;
wire   [31:0] index_assign_11_fu_1586_p1;
wire   [0:0] tmp_32_fu_1589_p3;
wire   [0:0] sel_tmp83_fu_1613_p2;
wire   [0:0] sel_tmp84_fu_1618_p2;
wire   [0:0] sel_tmp85_fu_1623_p2;
wire   [1:0] storemerge2_11_fu_1605_p3;
wire   [0:0] sel_tmp87_fu_1636_p2;
wire   [0:0] sel_tmp88_fu_1641_p2;
wire   [0:0] sel_tmp89_fu_1646_p2;
wire   [1:0] storemerge1_11_fu_1597_p3;
wire   [1:0] sel_tmp86_fu_1629_p3;
wire   [31:0] index_assign_12_fu_1669_p1;
wire   [0:0] tmp_33_fu_1672_p3;
wire   [0:0] sel_tmp90_fu_1696_p2;
wire   [0:0] sel_tmp91_fu_1701_p2;
wire   [0:0] sel_tmp92_fu_1706_p2;
wire   [1:0] storemerge2_12_fu_1688_p3;
wire   [0:0] sel_tmp94_fu_1719_p2;
wire   [0:0] sel_tmp95_fu_1724_p2;
wire   [0:0] sel_tmp96_fu_1729_p2;
wire   [1:0] storemerge1_12_fu_1680_p3;
wire   [1:0] sel_tmp93_fu_1712_p3;
wire   [31:0] index_assign_13_fu_1752_p1;
wire   [0:0] tmp_34_fu_1755_p3;
wire   [0:0] sel_tmp97_fu_1779_p2;
wire   [0:0] sel_tmp98_fu_1784_p2;
wire   [0:0] sel_tmp99_fu_1789_p2;
wire   [1:0] storemerge2_13_fu_1771_p3;
wire   [0:0] sel_tmp101_fu_1802_p2;
wire   [0:0] sel_tmp102_fu_1807_p2;
wire   [0:0] sel_tmp103_fu_1812_p2;
wire   [1:0] storemerge1_13_fu_1763_p3;
wire   [1:0] sel_tmp100_fu_1795_p3;
wire   [1:0] viterbiDecoder_state_V_load_15_fu_1818_p3;
wire   [31:0] index_assign_14_fu_1830_p1;
reg   [0:0] ap_NS_fsm;
reg    ap_sig_pprstidle_pp0;

// power-on initialization
initial begin
#0 ap_CS_fsm = 1'b1;
#0 ap_reg_ppiten_pp0_it1 = 1'b0;
#0 ap_reg_ppiten_pp0_it2 = 1'b0;
#0 ap_reg_ppiten_pp0_it3 = 1'b0;
#0 ap_reg_ppiten_pp0_it4 = 1'b0;
#0 ap_reg_ppiten_pp0_it5 = 1'b0;
#0 ap_reg_ppiten_pp0_it6 = 1'b0;
#0 ap_reg_ppiten_pp0_it7 = 1'b0;
#0 ap_reg_ppiten_pp0_it8 = 1'b0;
#0 ap_reg_ppiten_pp0_it9 = 1'b0;
#0 ap_reg_ppiten_pp0_it10 = 1'b0;
#0 ap_reg_ppiten_pp0_it11 = 1'b0;
#0 ap_reg_ppiten_pp0_it12 = 1'b0;
#0 ap_reg_ppiten_pp0_it13 = 1'b0;
#0 ap_reg_ppiten_pp0_it14 = 1'b0;
#0 ap_reg_ppiten_pp0_it15 = 1'b0;
#0 ap_reg_ppiten_pp0_it16 = 1'b0;
#0 ap_reg_ppiten_pp0_it17 = 1'b0;
#0 viterbiDecoder_distance_V_0 = 4'b0000;
#0 viterbiDecoder_distance_V_1 = 4'b0000;
#0 viterbiDecoder_distance_V_2 = 4'b0000;
#0 viterbiDecoder_distance_V_3 = 4'b0000;
#0 viterbiDecoder_globalDistance_3 = 4'b0000;
#0 viterbiDecoder_globalDistance_1 = 4'b10;
#0 viterbiDecoder_survivors_V = 4'b0000;
#0 viterbiDecoder_globalDistance_2 = 4'b10;
#0 viterbiDecoder_globalDistance_s = 4'b10;
#0 viterbiDecoder_survivorWindow_14 = 4'b0000;
#0 viterbiDecoder_survivorWindow_7 = 4'b0000;
#0 viterbiDecoder_survivorWindow_6 = 4'b0000;
#0 viterbiDecoder_survivorWindow_5 = 4'b0000;
#0 viterbiDecoder_survivorWindow_4 = 4'b0000;
#0 viterbiDecoder_survivorWindow_3 = 4'b0000;
#0 viterbiDecoder_survivorWindow_2 = 4'b0000;
#0 viterbiDecoder_survivorWindow_1 = 4'b0000;
#0 viterbiDecoder_survivorWindow_s = 4'b0000;
#0 viterbiDecoder_survivorWindow_13 = 4'b0000;
#0 viterbiDecoder_survivorWindow_12 = 4'b0000;
#0 viterbiDecoder_survivorWindow_11 = 4'b0000;
#0 viterbiDecoder_survivorWindow_10 = 4'b0000;
#0 viterbiDecoder_survivorWindow_9 = 4'b0000;
#0 viterbiDecoder_survivorWindow_8 = 4'b0000;
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it1 <= 1'b0;
    end else begin
        if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
            ap_reg_ppiten_pp0_it1 <= ap_start;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it10 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it11 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it12 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it13 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it14 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it15 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it16 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it17 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it2 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it3 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it4 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it5 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it6 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it7 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it8 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it9 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
        end
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_0))) begin
                viterbiDecoder_distance_V_0[0] <= 1'b0;
        viterbiDecoder_distance_V_0[1] <= 1'b0;
    end else if ((((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_2)) | ((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_1)))) begin
                viterbiDecoder_distance_V_0[0] <= 1'b1;
        viterbiDecoder_distance_V_0[1] <= 1'b0;
    end else if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_3))) begin
                viterbiDecoder_distance_V_0[0] <= 1'b0;
        viterbiDecoder_distance_V_0[1] <= 1'b1;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_1))) begin
                viterbiDecoder_distance_V_1[0] <= 1'b0;
        viterbiDecoder_distance_V_1[1] <= 1'b0;
    end else if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_2))) begin
                viterbiDecoder_distance_V_1[0] <= 1'b0;
        viterbiDecoder_distance_V_1[1] <= 1'b1;
    end else if ((((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_3)) | ((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_0)))) begin
                viterbiDecoder_distance_V_1[0] <= 1'b1;
        viterbiDecoder_distance_V_1[1] <= 1'b0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_1))) begin
                viterbiDecoder_distance_V_2[0] <= 1'b0;
        viterbiDecoder_distance_V_2[1] <= 1'b1;
    end else if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_2))) begin
                viterbiDecoder_distance_V_2[0] <= 1'b0;
        viterbiDecoder_distance_V_2[1] <= 1'b0;
    end else if ((((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_3)) | ((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_0)))) begin
                viterbiDecoder_distance_V_2[0] <= 1'b1;
        viterbiDecoder_distance_V_2[1] <= 1'b0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_0))) begin
                viterbiDecoder_distance_V_3[0] <= 1'b0;
        viterbiDecoder_distance_V_3[1] <= 1'b1;
    end else if ((((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_2)) | ((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_1)))) begin
                viterbiDecoder_distance_V_3[0] <= 1'b1;
        viterbiDecoder_distance_V_3[1] <= 1'b0;
    end else if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)) & (indat_V_read_read_fu_90_p2 == ap_const_lv2_3))) begin
                viterbiDecoder_distance_V_3[0] <= 1'b0;
        viterbiDecoder_distance_V_3[1] <= 1'b0;
    end
end

always @ (posedge ap_clk) begin
    if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
        ap_reg_ppstg_tmp_25_2_reg_1887_pp0_iter2 <= tmp_25_2_reg_1887;
        ap_reg_ppstg_viterbiDecoder_survivorWindow_15_reg_1894_pp0_iter3 <= viterbiDecoder_survivorWindow_15_reg_1894;
        p_viterbiDecoder_state_V_load_s_reg_1899 <= p_viterbiDecoder_state_V_load_s_fu_594_p3;
        tmp_20_reg_1907 <= tmp_20_fu_606_p3;
        viterbiDecoder_state_V_load_10_reg_2048 <= viterbiDecoder_state_V_load_10_fu_1403_p3;
        viterbiDecoder_state_V_load_11_reg_2063 <= viterbiDecoder_state_V_load_11_fu_1486_p3;
        viterbiDecoder_state_V_load_12_reg_2078 <= viterbiDecoder_state_V_load_12_fu_1569_p3;
        viterbiDecoder_state_V_load_13_reg_2093 <= viterbiDecoder_state_V_load_13_fu_1652_p3;
        viterbiDecoder_state_V_load_14_reg_2108 <= viterbiDecoder_state_V_load_14_fu_1735_p3;
        viterbiDecoder_state_V_load_1_reg_1913 <= viterbiDecoder_state_V_load_1_fu_661_p3;
        viterbiDecoder_state_V_load_2_reg_1928 <= viterbiDecoder_state_V_load_2_fu_739_p3;
        viterbiDecoder_state_V_load_3_reg_1943 <= viterbiDecoder_state_V_load_3_fu_822_p3;
        viterbiDecoder_state_V_load_4_reg_1958 <= viterbiDecoder_state_V_load_4_fu_905_p3;
        viterbiDecoder_state_V_load_5_reg_1973 <= viterbiDecoder_state_V_load_5_fu_988_p3;
        viterbiDecoder_state_V_load_6_reg_1988 <= viterbiDecoder_state_V_load_6_fu_1071_p3;
        viterbiDecoder_state_V_load_7_reg_2003 <= viterbiDecoder_state_V_load_7_fu_1154_p3;
        viterbiDecoder_state_V_load_8_reg_2018 <= viterbiDecoder_state_V_load_8_fu_1237_p3;
        viterbiDecoder_state_V_load_9_reg_2033 <= viterbiDecoder_state_V_load_9_fu_1320_p3;
        viterbiDecoder_survivorWindow_10_reg_2073 <= viterbiDecoder_survivorWindow_12;
        viterbiDecoder_survivorWindow_11_reg_2088 <= viterbiDecoder_survivorWindow_11;
        viterbiDecoder_survivorWindow_12_reg_2103 <= viterbiDecoder_survivorWindow_10;
        viterbiDecoder_survivorWindow_15_reg_1894 <= viterbiDecoder_survivorWindow_15_fu_567_p3;
        viterbiDecoder_survivorWindow_1_reg_1938 <= viterbiDecoder_survivorWindow_7;
        viterbiDecoder_survivorWindow_2_reg_1953 <= viterbiDecoder_survivorWindow_6;
        viterbiDecoder_survivorWindow_3_reg_1968 <= viterbiDecoder_survivorWindow_5;
        viterbiDecoder_survivorWindow_4_reg_1983 <= viterbiDecoder_survivorWindow_4;
        viterbiDecoder_survivorWindow_5_reg_1998 <= viterbiDecoder_survivorWindow_3;
        viterbiDecoder_survivorWindow_6_reg_2013 <= viterbiDecoder_survivorWindow_2;
        viterbiDecoder_survivorWindow_7_reg_2028 <= viterbiDecoder_survivorWindow_1;
        viterbiDecoder_survivorWindow_8_reg_2043 <= viterbiDecoder_survivorWindow_s;
        viterbiDecoder_survivorWindow_9_reg_2058 <= viterbiDecoder_survivorWindow_13;
        viterbiDecoder_survivorWindow_s_reg_1923 <= viterbiDecoder_survivorWindow_14;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        tmp_25_1_reg_1882 <= tmp_25_1_fu_350_p2;
        tmp_25_2_reg_1887 <= tmp_25_2_fu_364_p2;
        tmp_27_1_reg_1862 <= tmp_27_1_fu_238_p2;
        tmp_27_2_reg_1867 <= tmp_27_2_fu_296_p2;
        tmp_27_3_reg_1872 <= tmp_27_3_fu_322_p2;
        tmp_9_reg_1877 <= tmp_9_fu_336_p2;
        tmp_s_reg_1857 <= tmp_s_fu_212_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it1) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_globalDistance_1 <= r_V_2_fu_418_p2;
        viterbiDecoder_globalDistance_2 <= r_V_1_fu_402_p2;
        viterbiDecoder_globalDistance_3 <= r_V_fu_386_p2;
        viterbiDecoder_globalDistance_s <= r_V_3_fu_434_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it11) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_1 <= viterbiDecoder_survivorWindow_6_reg_2013;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it16) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_10 <= viterbiDecoder_survivorWindow_11_reg_2088;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it15) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_11 <= viterbiDecoder_survivorWindow_10_reg_2073;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it14) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_12 <= viterbiDecoder_survivorWindow_9_reg_2058;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it13) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_13 <= viterbiDecoder_survivorWindow_8_reg_2043;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it4) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_14 <= ap_reg_ppstg_viterbiDecoder_survivorWindow_15_reg_1894_pp0_iter3;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it10) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_2 <= viterbiDecoder_survivorWindow_5_reg_1998;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it9) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_3 <= viterbiDecoder_survivorWindow_4_reg_1983;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it8) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_4 <= viterbiDecoder_survivorWindow_3_reg_1968;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it7) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_5 <= viterbiDecoder_survivorWindow_2_reg_1953;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it6) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_6 <= viterbiDecoder_survivorWindow_1_reg_1938;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it5) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_7 <= viterbiDecoder_survivorWindow_s_reg_1923;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it17) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_8 <= viterbiDecoder_survivorWindow_9;
        viterbiDecoder_survivorWindow_9 <= viterbiDecoder_survivorWindow_12_reg_2103;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it12) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivorWindow_s <= viterbiDecoder_survivorWindow_7_reg_2028;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it2) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        viterbiDecoder_survivors_V <= viterbiDecoder_survivorWindow_15_fu_567_p3;
    end
end

always @ (*) begin
    if ((((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0)) | ((1'b1 == ap_reg_ppiten_pp0_it17) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2) & (1'b0 == ap_reg_ppiten_pp0_it3) & (1'b0 == ap_reg_ppiten_pp0_it4) & (1'b0 == ap_reg_ppiten_pp0_it5) & (1'b0 == ap_reg_ppiten_pp0_it6) & (1'b0 == ap_reg_ppiten_pp0_it7) & (1'b0 == ap_reg_ppiten_pp0_it8) & (1'b0 == ap_reg_ppiten_pp0_it9) & (1'b0 == ap_reg_ppiten_pp0_it10) & (1'b0 == ap_reg_ppiten_pp0_it11) & (1'b0 == ap_reg_ppiten_pp0_it12) & (1'b0 == ap_reg_ppiten_pp0_it13) & (1'b0 == ap_reg_ppiten_pp0_it14) & (1'b0 == ap_reg_ppiten_pp0_it15) & (1'b0 == ap_reg_ppiten_pp0_it16) & (1'b0 == ap_reg_ppiten_pp0_it17))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_18) begin
        ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b1;
    end else begin
        ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2) & (1'b0 == ap_reg_ppiten_pp0_it3) & (1'b0 == ap_reg_ppiten_pp0_it4) & (1'b0 == ap_reg_ppiten_pp0_it5) & (1'b0 == ap_reg_ppiten_pp0_it6) & (1'b0 == ap_reg_ppiten_pp0_it7) & (1'b0 == ap_reg_ppiten_pp0_it8) & (1'b0 == ap_reg_ppiten_pp0_it9) & (1'b0 == ap_reg_ppiten_pp0_it10) & (1'b0 == ap_reg_ppiten_pp0_it11) & (1'b0 == ap_reg_ppiten_pp0_it12) & (1'b0 == ap_reg_ppiten_pp0_it13) & (1'b0 == ap_reg_ppiten_pp0_it14) & (1'b0 == ap_reg_ppiten_pp0_it15) & (1'b0 == ap_reg_ppiten_pp0_it16))) begin
        ap_sig_pprstidle_pp0 = 1'b1;
    end else begin
        ap_sig_pprstidle_pp0 = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_pp0_stg0_fsm_0 : begin
            ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_reg_ppiten_pp0_it0 = ap_start;

assign ap_return = viterbiDecoder_survivorWindow_8[index_assign_14_fu_1830_p1];

always @ (*) begin
    ap_sig_18 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end

assign indat_V_read_read_fu_90_p2 = indat_V;

assign index_assign_10_fu_1503_p1 = viterbiDecoder_state_V_load_11_reg_2063;

assign index_assign_11_fu_1586_p1 = viterbiDecoder_state_V_load_12_reg_2078;

assign index_assign_12_fu_1669_p1 = viterbiDecoder_state_V_load_13_reg_2093;

assign index_assign_13_fu_1752_p1 = viterbiDecoder_state_V_load_14_reg_2108;

assign index_assign_14_fu_1830_p1 = viterbiDecoder_state_V_load_15_fu_1818_p3;

assign index_assign_1_fu_673_p1 = viterbiDecoder_state_V_load_1_reg_1913;

assign index_assign_2_fu_756_p1 = viterbiDecoder_state_V_load_2_reg_1928;

assign index_assign_3_fu_839_p1 = viterbiDecoder_state_V_load_3_reg_1943;

assign index_assign_4_fu_922_p1 = viterbiDecoder_state_V_load_4_reg_1958;

assign index_assign_5_fu_1005_p1 = viterbiDecoder_state_V_load_5_reg_1973;

assign index_assign_6_fu_1088_p1 = viterbiDecoder_state_V_load_6_reg_1988;

assign index_assign_7_fu_1171_p1 = viterbiDecoder_state_V_load_7_reg_2003;

assign index_assign_8_fu_1254_p1 = viterbiDecoder_state_V_load_8_reg_2018;

assign index_assign_9_fu_1337_p1 = viterbiDecoder_state_V_load_9_reg_2033;

assign index_assign_fu_602_p1 = p_viterbiDecoder_state_V_load_s_fu_594_p3;

assign index_assign_s_fu_1420_p1 = viterbiDecoder_state_V_load_10_reg_2048;

assign lhs_V_1_fu_398_p1 = viterbiDecoder_branchDistance_1_fu_244_p3;

assign lhs_V_2_fu_414_p1 = viterbiDecoder_branchDistance_2_fu_302_p3;

assign lhs_V_3_fu_430_p1 = viterbiDecoder_branchDistance_3_fu_328_p3;

assign lhs_V_fu_378_p1 = viterbiDecoder_branchDistance_s_fu_218_p3;

assign p_s_fu_580_p1 = tmp_9_reg_1877;

assign p_viterbiDecoder_state_V_load_s_fu_594_p3 = ((tmp_fu_590_p2[0:0] === 1'b1) ? viterbiDecoder_state_V_load_s_fu_583_p3 : p_s_fu_580_p1);

assign r_V_1_fu_402_p2 = (lhs_V_1_fu_398_p1 - rhs_V_fu_382_p1);

assign r_V_2_fu_418_p2 = (lhs_V_2_fu_414_p1 - rhs_V_fu_382_p1);

assign r_V_3_fu_434_p2 = (lhs_V_3_fu_430_p1 - rhs_V_fu_382_p1);

assign r_V_fu_386_p2 = (lhs_V_fu_378_p1 - rhs_V_fu_382_p1);

assign rhs_V_fu_382_p1 = sel_SEBB1_fu_370_p3;

assign sel_SEBB1_fu_370_p3 = ((tmp_25_2_fu_364_p2[0:0] === 1'b1) ? viterbiDecoder_branchDistance_3_fu_328_p3 : viterbiDecoder_minimumBranch_V_fu_356_p3);

assign sel_SEBB_fu_342_p3 = ((tmp_9_fu_336_p2[0:0] === 1'b1) ? viterbiDecoder_branchDistance_1_fu_244_p3 : viterbiDecoder_branchDistance_s_fu_218_p3);

assign sel_tmp100_fu_1795_p3 = ((sel_tmp99_fu_1789_p2[0:0] === 1'b1) ? storemerge2_13_fu_1771_p3 : viterbiDecoder_state_V_load_14_reg_2108);

assign sel_tmp101_fu_1802_p2 = ((viterbiDecoder_state_V_load_14_reg_2108 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp102_fu_1807_p2 = ((viterbiDecoder_state_V_load_14_reg_2108 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp103_fu_1812_p2 = (sel_tmp101_fu_1802_p2 | sel_tmp102_fu_1807_p2);

assign sel_tmp10_fu_723_p2 = ((viterbiDecoder_state_V_load_1_reg_1913 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp11_fu_728_p2 = ((viterbiDecoder_state_V_load_1_reg_1913 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp12_fu_733_p2 = (sel_tmp10_fu_723_p2 | sel_tmp11_fu_728_p2);

assign sel_tmp13_fu_783_p2 = ((viterbiDecoder_state_V_load_2_reg_1928 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp14_fu_788_p2 = ((viterbiDecoder_state_V_load_2_reg_1928 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp15_fu_793_p2 = (sel_tmp13_fu_783_p2 | sel_tmp14_fu_788_p2);

assign sel_tmp16_fu_799_p3 = ((sel_tmp15_fu_793_p2[0:0] === 1'b1) ? storemerge2_2_fu_775_p3 : viterbiDecoder_state_V_load_2_reg_1928);

assign sel_tmp17_fu_806_p2 = ((viterbiDecoder_state_V_load_2_reg_1928 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp18_fu_811_p2 = ((viterbiDecoder_state_V_load_2_reg_1928 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp19_fu_816_p2 = (sel_tmp17_fu_806_p2 | sel_tmp18_fu_811_p2);

assign sel_tmp1_fu_710_p2 = (sel_tmp8_fu_700_p2 | sel_tmp9_fu_705_p2);

assign sel_tmp20_fu_866_p2 = ((viterbiDecoder_state_V_load_3_reg_1943 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp21_fu_871_p2 = ((viterbiDecoder_state_V_load_3_reg_1943 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp22_fu_876_p2 = (sel_tmp20_fu_866_p2 | sel_tmp21_fu_871_p2);

assign sel_tmp23_fu_882_p3 = ((sel_tmp22_fu_876_p2[0:0] === 1'b1) ? storemerge2_3_fu_858_p3 : viterbiDecoder_state_V_load_3_reg_1943);

assign sel_tmp24_fu_889_p2 = ((viterbiDecoder_state_V_load_3_reg_1943 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp25_fu_894_p2 = ((viterbiDecoder_state_V_load_3_reg_1943 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp26_fu_899_p2 = (sel_tmp24_fu_889_p2 | sel_tmp25_fu_894_p2);

assign sel_tmp27_fu_949_p2 = ((viterbiDecoder_state_V_load_4_reg_1958 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp28_fu_954_p2 = ((viterbiDecoder_state_V_load_4_reg_1958 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp29_fu_959_p2 = (sel_tmp27_fu_949_p2 | sel_tmp28_fu_954_p2);

assign sel_tmp2_fu_633_p2 = (sel_tmp_fu_628_p2 | ap_reg_ppstg_tmp_25_2_reg_1887_pp0_iter2);

assign sel_tmp30_fu_965_p3 = ((sel_tmp29_fu_959_p2[0:0] === 1'b1) ? storemerge2_4_fu_941_p3 : viterbiDecoder_state_V_load_4_reg_1958);

assign sel_tmp31_fu_972_p2 = ((viterbiDecoder_state_V_load_4_reg_1958 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp32_fu_977_p2 = ((viterbiDecoder_state_V_load_4_reg_1958 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp33_fu_982_p2 = (sel_tmp31_fu_972_p2 | sel_tmp32_fu_977_p2);

assign sel_tmp34_fu_1032_p2 = ((viterbiDecoder_state_V_load_5_reg_1973 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp35_fu_1037_p2 = ((viterbiDecoder_state_V_load_5_reg_1973 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp36_fu_1042_p2 = (sel_tmp34_fu_1032_p2 | sel_tmp35_fu_1037_p2);

assign sel_tmp37_fu_1048_p3 = ((sel_tmp36_fu_1042_p2[0:0] === 1'b1) ? storemerge2_5_fu_1024_p3 : viterbiDecoder_state_V_load_5_reg_1973);

assign sel_tmp38_fu_1055_p2 = ((viterbiDecoder_state_V_load_5_reg_1973 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp39_fu_1060_p2 = ((viterbiDecoder_state_V_load_5_reg_1973 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp3_fu_638_p3 = ((sel_tmp2_fu_633_p2[0:0] === 1'b1) ? storemerge2_fu_621_p3 : p_viterbiDecoder_state_V_load_s_reg_1899);

assign sel_tmp40_fu_1065_p2 = (sel_tmp38_fu_1055_p2 | sel_tmp39_fu_1060_p2);

assign sel_tmp41_fu_1115_p2 = ((viterbiDecoder_state_V_load_6_reg_1988 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp42_fu_1120_p2 = ((viterbiDecoder_state_V_load_6_reg_1988 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp43_fu_1125_p2 = (sel_tmp41_fu_1115_p2 | sel_tmp42_fu_1120_p2);

assign sel_tmp44_fu_1131_p3 = ((sel_tmp43_fu_1125_p2[0:0] === 1'b1) ? storemerge2_6_fu_1107_p3 : viterbiDecoder_state_V_load_6_reg_1988);

assign sel_tmp45_fu_1138_p2 = ((viterbiDecoder_state_V_load_6_reg_1988 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp46_fu_1143_p2 = ((viterbiDecoder_state_V_load_6_reg_1988 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp47_fu_1148_p2 = (sel_tmp45_fu_1138_p2 | sel_tmp46_fu_1143_p2);

assign sel_tmp48_fu_1198_p2 = ((viterbiDecoder_state_V_load_7_reg_2003 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp49_fu_1203_p2 = ((viterbiDecoder_state_V_load_7_reg_2003 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp4_fu_645_p2 = ((p_viterbiDecoder_state_V_load_s_reg_1899 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp50_fu_1208_p2 = (sel_tmp48_fu_1198_p2 | sel_tmp49_fu_1203_p2);

assign sel_tmp51_fu_1214_p3 = ((sel_tmp50_fu_1208_p2[0:0] === 1'b1) ? storemerge2_7_fu_1190_p3 : viterbiDecoder_state_V_load_7_reg_2003);

assign sel_tmp52_fu_1221_p2 = ((viterbiDecoder_state_V_load_7_reg_2003 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp53_fu_1226_p2 = ((viterbiDecoder_state_V_load_7_reg_2003 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp54_fu_1231_p2 = (sel_tmp52_fu_1221_p2 | sel_tmp53_fu_1226_p2);

assign sel_tmp55_fu_1281_p2 = ((viterbiDecoder_state_V_load_8_reg_2018 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp56_fu_1286_p2 = ((viterbiDecoder_state_V_load_8_reg_2018 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp57_fu_1291_p2 = (sel_tmp55_fu_1281_p2 | sel_tmp56_fu_1286_p2);

assign sel_tmp58_fu_1297_p3 = ((sel_tmp57_fu_1291_p2[0:0] === 1'b1) ? storemerge2_8_fu_1273_p3 : viterbiDecoder_state_V_load_8_reg_2018);

assign sel_tmp59_fu_1304_p2 = ((viterbiDecoder_state_V_load_8_reg_2018 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp5_fu_650_p2 = ((p_viterbiDecoder_state_V_load_s_reg_1899 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp60_fu_1309_p2 = ((viterbiDecoder_state_V_load_8_reg_2018 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp61_fu_1314_p2 = (sel_tmp59_fu_1304_p2 | sel_tmp60_fu_1309_p2);

assign sel_tmp62_fu_1364_p2 = ((viterbiDecoder_state_V_load_9_reg_2033 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp63_fu_1369_p2 = ((viterbiDecoder_state_V_load_9_reg_2033 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp64_fu_1374_p2 = (sel_tmp62_fu_1364_p2 | sel_tmp63_fu_1369_p2);

assign sel_tmp65_fu_1380_p3 = ((sel_tmp64_fu_1374_p2[0:0] === 1'b1) ? storemerge2_9_fu_1356_p3 : viterbiDecoder_state_V_load_9_reg_2033);

assign sel_tmp66_fu_1387_p2 = ((viterbiDecoder_state_V_load_9_reg_2033 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp67_fu_1392_p2 = ((viterbiDecoder_state_V_load_9_reg_2033 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp68_fu_1397_p2 = (sel_tmp66_fu_1387_p2 | sel_tmp67_fu_1392_p2);

assign sel_tmp69_fu_1447_p2 = ((viterbiDecoder_state_V_load_10_reg_2048 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp6_fu_655_p2 = (sel_tmp4_fu_645_p2 | sel_tmp5_fu_650_p2);

assign sel_tmp70_fu_1452_p2 = ((viterbiDecoder_state_V_load_10_reg_2048 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp71_fu_1457_p2 = (sel_tmp69_fu_1447_p2 | sel_tmp70_fu_1452_p2);

assign sel_tmp72_fu_1463_p3 = ((sel_tmp71_fu_1457_p2[0:0] === 1'b1) ? storemerge2_s_fu_1439_p3 : viterbiDecoder_state_V_load_10_reg_2048);

assign sel_tmp73_fu_1470_p2 = ((viterbiDecoder_state_V_load_10_reg_2048 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp74_fu_1475_p2 = ((viterbiDecoder_state_V_load_10_reg_2048 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp75_fu_1480_p2 = (sel_tmp73_fu_1470_p2 | sel_tmp74_fu_1475_p2);

assign sel_tmp76_fu_1530_p2 = ((viterbiDecoder_state_V_load_11_reg_2063 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp77_fu_1535_p2 = ((viterbiDecoder_state_V_load_11_reg_2063 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp78_fu_1540_p2 = (sel_tmp76_fu_1530_p2 | sel_tmp77_fu_1535_p2);

assign sel_tmp79_fu_1546_p3 = ((sel_tmp78_fu_1540_p2[0:0] === 1'b1) ? storemerge2_10_fu_1522_p3 : viterbiDecoder_state_V_load_11_reg_2063);

assign sel_tmp7_fu_716_p3 = ((sel_tmp1_fu_710_p2[0:0] === 1'b1) ? storemerge2_1_fu_692_p3 : viterbiDecoder_state_V_load_1_reg_1913);

assign sel_tmp80_fu_1553_p2 = ((viterbiDecoder_state_V_load_11_reg_2063 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp81_fu_1558_p2 = ((viterbiDecoder_state_V_load_11_reg_2063 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp82_fu_1563_p2 = (sel_tmp80_fu_1553_p2 | sel_tmp81_fu_1558_p2);

assign sel_tmp83_fu_1613_p2 = ((viterbiDecoder_state_V_load_12_reg_2078 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp84_fu_1618_p2 = ((viterbiDecoder_state_V_load_12_reg_2078 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp85_fu_1623_p2 = (sel_tmp83_fu_1613_p2 | sel_tmp84_fu_1618_p2);

assign sel_tmp86_fu_1629_p3 = ((sel_tmp85_fu_1623_p2[0:0] === 1'b1) ? storemerge2_11_fu_1605_p3 : viterbiDecoder_state_V_load_12_reg_2078);

assign sel_tmp87_fu_1636_p2 = ((viterbiDecoder_state_V_load_12_reg_2078 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp88_fu_1641_p2 = ((viterbiDecoder_state_V_load_12_reg_2078 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp89_fu_1646_p2 = (sel_tmp87_fu_1636_p2 | sel_tmp88_fu_1641_p2);

assign sel_tmp8_fu_700_p2 = ((viterbiDecoder_state_V_load_1_reg_1913 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp90_fu_1696_p2 = ((viterbiDecoder_state_V_load_13_reg_2093 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp91_fu_1701_p2 = ((viterbiDecoder_state_V_load_13_reg_2093 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp92_fu_1706_p2 = (sel_tmp90_fu_1696_p2 | sel_tmp91_fu_1701_p2);

assign sel_tmp93_fu_1712_p3 = ((sel_tmp92_fu_1706_p2[0:0] === 1'b1) ? storemerge2_12_fu_1688_p3 : viterbiDecoder_state_V_load_13_reg_2093);

assign sel_tmp94_fu_1719_p2 = ((viterbiDecoder_state_V_load_13_reg_2093 == ap_const_lv2_0) ? 1'b1 : 1'b0);

assign sel_tmp95_fu_1724_p2 = ((viterbiDecoder_state_V_load_13_reg_2093 == ap_const_lv2_1) ? 1'b1 : 1'b0);

assign sel_tmp96_fu_1729_p2 = (sel_tmp94_fu_1719_p2 | sel_tmp95_fu_1724_p2);

assign sel_tmp97_fu_1779_p2 = ((viterbiDecoder_state_V_load_14_reg_2108 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign sel_tmp98_fu_1784_p2 = ((viterbiDecoder_state_V_load_14_reg_2108 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp99_fu_1789_p2 = (sel_tmp97_fu_1779_p2 | sel_tmp98_fu_1784_p2);

assign sel_tmp9_fu_705_p2 = ((viterbiDecoder_state_V_load_1_reg_1913 == ap_const_lv2_3) ? 1'b1 : 1'b0);

assign sel_tmp_fu_628_p2 = ((p_viterbiDecoder_state_V_load_s_reg_1899 == ap_const_lv2_2) ? 1'b1 : 1'b0);

assign storemerge1_10_fu_1514_p3 = ((tmp_31_fu_1506_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_11_fu_1597_p3 = ((tmp_32_fu_1589_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_12_fu_1680_p3 = ((tmp_33_fu_1672_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_13_fu_1763_p3 = ((tmp_34_fu_1755_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_1_fu_684_p3 = ((tmp_21_fu_676_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_2_fu_767_p3 = ((tmp_22_fu_759_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_3_fu_850_p3 = ((tmp_23_fu_842_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_4_fu_933_p3 = ((tmp_24_fu_925_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_5_fu_1016_p3 = ((tmp_25_fu_1008_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_6_fu_1099_p3 = ((tmp_26_fu_1091_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_7_fu_1182_p3 = ((tmp_27_fu_1174_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_8_fu_1265_p3 = ((tmp_28_fu_1257_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_9_fu_1348_p3 = ((tmp_29_fu_1340_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_fu_614_p3 = ((tmp_20_reg_1907[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge1_s_fu_1431_p3 = ((tmp_30_fu_1423_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);

assign storemerge2_10_fu_1522_p3 = ((tmp_31_fu_1506_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_11_fu_1605_p3 = ((tmp_32_fu_1589_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_12_fu_1688_p3 = ((tmp_33_fu_1672_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_13_fu_1771_p3 = ((tmp_34_fu_1755_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_1_fu_692_p3 = ((tmp_21_fu_676_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_2_fu_775_p3 = ((tmp_22_fu_759_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_3_fu_858_p3 = ((tmp_23_fu_842_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_4_fu_941_p3 = ((tmp_24_fu_925_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_5_fu_1024_p3 = ((tmp_25_fu_1008_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_6_fu_1107_p3 = ((tmp_26_fu_1091_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_7_fu_1190_p3 = ((tmp_27_fu_1174_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_8_fu_1273_p3 = ((tmp_28_fu_1257_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_9_fu_1356_p3 = ((tmp_29_fu_1340_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_fu_621_p3 = ((tmp_20_reg_1907[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign storemerge2_s_fu_1439_p3 = ((tmp_30_fu_1423_p3[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_1);

assign tmp_10_fu_450_p4 = {{viterbiDecoder_survivors_V[ap_const_lv32_3 : ap_const_lv32_1]}};

assign tmp_11_1_fu_232_p2 = (tmp_1_fu_172_p1 + tmp_5_fu_202_p1);

assign tmp_11_fu_481_p4 = {{viterbiDecoder_survivors_V_loa_1_fu_474_p3[ap_const_lv32_3 : ap_const_lv32_2]}};

assign tmp_12_fu_491_p1 = viterbiDecoder_survivors_V_loa_1_fu_474_p3[0:0];

assign tmp_13_fu_256_p1 = viterbiDecoder_distance_V_1[2:0];

assign tmp_14_2_fu_268_p2 = (tmp_13_fu_256_p1 + tmp_14_fu_264_p1);

assign tmp_14_fu_264_p1 = viterbiDecoder_globalDistance_2[2:0];

assign tmp_15_fu_278_p1 = viterbiDecoder_distance_V_2[2:0];

assign tmp_16_fu_286_p1 = viterbiDecoder_globalDistance_s[2:0];

assign tmp_17_2_fu_290_p2 = (tmp_15_fu_278_p1 + tmp_16_fu_286_p1);

assign tmp_17_fu_518_p3 = viterbiDecoder_survivors_V_loa_2_fu_511_p3[ap_const_lv32_3];

assign tmp_18_fu_526_p1 = viterbiDecoder_survivors_V_loa_2_fu_511_p3[1:0];

assign tmp_19_fu_553_p1 = viterbiDecoder_survivors_V_loa_3_fu_546_p3[2:0];

assign tmp_1_fu_172_p1 = viterbiDecoder_distance_V_0[2:0];

assign tmp_20_3_fu_310_p2 = (tmp_15_fu_278_p1 + tmp_14_fu_264_p1);

assign tmp_20_fu_606_p3 = viterbiDecoder_survivorWindow_15_fu_567_p3[index_assign_fu_602_p1];

assign tmp_21_fu_676_p3 = viterbiDecoder_survivorWindow_14[index_assign_1_fu_673_p1];

assign tmp_22_fu_759_p3 = viterbiDecoder_survivorWindow_7[index_assign_2_fu_756_p1];

assign tmp_23_3_fu_316_p2 = (tmp_13_fu_256_p1 + tmp_16_fu_286_p1);

assign tmp_23_fu_842_p3 = viterbiDecoder_survivorWindow_6[index_assign_3_fu_839_p1];

assign tmp_24_fu_925_p3 = viterbiDecoder_survivorWindow_5[index_assign_4_fu_922_p1];

assign tmp_25_1_fu_350_p2 = ((viterbiDecoder_branchDistance_2_fu_302_p3 < sel_SEBB_fu_342_p3) ? 1'b1 : 1'b0);

assign tmp_25_2_fu_364_p2 = ((viterbiDecoder_branchDistance_3_fu_328_p3 < viterbiDecoder_minimumBranch_V_fu_356_p3) ? 1'b1 : 1'b0);

assign tmp_25_fu_1008_p3 = viterbiDecoder_survivorWindow_4[index_assign_5_fu_1005_p1];

assign tmp_26_fu_1091_p3 = viterbiDecoder_survivorWindow_3[index_assign_6_fu_1088_p1];

assign tmp_27_1_fu_238_p2 = ((tmp_9_1_fu_226_p2 > tmp_11_1_fu_232_p2) ? 1'b1 : 1'b0);

assign tmp_27_2_fu_296_p2 = ((tmp_14_2_fu_268_p2 > tmp_17_2_fu_290_p2) ? 1'b1 : 1'b0);

assign tmp_27_3_fu_322_p2 = ((tmp_20_3_fu_310_p2 > tmp_23_3_fu_316_p2) ? 1'b1 : 1'b0);

assign tmp_27_fu_1174_p3 = viterbiDecoder_survivorWindow_2[index_assign_7_fu_1171_p1];

assign tmp_28_fu_1257_p3 = viterbiDecoder_survivorWindow_1[index_assign_8_fu_1254_p1];

assign tmp_29_fu_1340_p3 = viterbiDecoder_survivorWindow_s[index_assign_9_fu_1337_p1];

assign tmp_2_fu_180_p1 = viterbiDecoder_globalDistance_3[2:0];

assign tmp_30_1_fu_505_p2 = (viterbiDecoder_survivors_V_loa_1_fu_474_p3 | ap_const_lv4_2);

assign tmp_30_2_fu_540_p2 = (viterbiDecoder_survivors_V_loa_2_fu_511_p3 | ap_const_lv4_4);

assign tmp_30_3_fu_561_p2 = (viterbiDecoder_survivors_V_loa_3_fu_546_p3 | ap_const_lv4_8);

assign tmp_30_fu_1423_p3 = viterbiDecoder_survivorWindow_13[index_assign_s_fu_1420_p1];

assign tmp_31_fu_1506_p3 = viterbiDecoder_survivorWindow_12[index_assign_10_fu_1503_p1];

assign tmp_32_fu_1589_p3 = viterbiDecoder_survivorWindow_11[index_assign_11_fu_1586_p1];

assign tmp_33_fu_1672_p3 = viterbiDecoder_survivorWindow_10[index_assign_12_fu_1669_p1];

assign tmp_34_1_fu_495_p4 = {{{tmp_11_fu_481_p4}, {1'b0}}, {tmp_12_fu_491_p1}};

assign tmp_34_2_fu_530_p4 = {{{tmp_17_fu_518_p3}, {1'b0}}, {tmp_18_fu_526_p1}};

assign tmp_34_3_cast_fu_557_p1 = tmp_19_fu_553_p1;

assign tmp_34_fu_1755_p3 = viterbiDecoder_survivorWindow_9[index_assign_13_fu_1752_p1];

assign tmp_3_fu_184_p2 = (tmp_2_fu_180_p1 + tmp_1_fu_172_p1);

assign tmp_4_fu_194_p1 = viterbiDecoder_distance_V_3[2:0];

assign tmp_5_fu_202_p1 = viterbiDecoder_globalDistance_1[2:0];

assign tmp_6_fu_206_p2 = (tmp_5_fu_202_p1 + tmp_4_fu_194_p1);

assign tmp_7_fu_460_p3 = {{tmp_10_fu_450_p4}, {1'b0}};

assign tmp_8_fu_468_p2 = (viterbiDecoder_survivors_V | ap_const_lv4_1);

assign tmp_9_1_fu_226_p2 = (tmp_4_fu_194_p1 + tmp_2_fu_180_p1);

assign tmp_9_fu_336_p2 = ((viterbiDecoder_branchDistance_1_fu_244_p3 < viterbiDecoder_branchDistance_s_fu_218_p3) ? 1'b1 : 1'b0);

assign tmp_fu_590_p2 = (tmp_25_2_reg_1887 | tmp_25_1_reg_1882);

assign tmp_s_fu_212_p2 = ((tmp_3_fu_184_p2 > tmp_6_fu_206_p2) ? 1'b1 : 1'b0);

assign viterbiDecoder_branchDistance_1_fu_244_p3 = ((tmp_27_1_fu_238_p2[0:0] === 1'b1) ? tmp_11_1_fu_232_p2 : tmp_9_1_fu_226_p2);

assign viterbiDecoder_branchDistance_2_fu_302_p3 = ((tmp_27_2_fu_296_p2[0:0] === 1'b1) ? tmp_17_2_fu_290_p2 : tmp_14_2_fu_268_p2);

assign viterbiDecoder_branchDistance_3_fu_328_p3 = ((tmp_27_3_fu_322_p2[0:0] === 1'b1) ? tmp_23_3_fu_316_p2 : tmp_20_3_fu_310_p2);

assign viterbiDecoder_branchDistance_s_fu_218_p3 = ((tmp_s_fu_212_p2[0:0] === 1'b1) ? tmp_6_fu_206_p2 : tmp_3_fu_184_p2);

assign viterbiDecoder_minimumBranch_V_fu_356_p3 = ((tmp_25_1_fu_350_p2[0:0] === 1'b1) ? viterbiDecoder_branchDistance_2_fu_302_p3 : sel_SEBB_fu_342_p3);

assign viterbiDecoder_state_V_load_10_fu_1403_p3 = ((sel_tmp68_fu_1397_p2[0:0] === 1'b1) ? storemerge1_9_fu_1348_p3 : sel_tmp65_fu_1380_p3);

assign viterbiDecoder_state_V_load_11_fu_1486_p3 = ((sel_tmp75_fu_1480_p2[0:0] === 1'b1) ? storemerge1_s_fu_1431_p3 : sel_tmp72_fu_1463_p3);

assign viterbiDecoder_state_V_load_12_fu_1569_p3 = ((sel_tmp82_fu_1563_p2[0:0] === 1'b1) ? storemerge1_10_fu_1514_p3 : sel_tmp79_fu_1546_p3);

assign viterbiDecoder_state_V_load_13_fu_1652_p3 = ((sel_tmp89_fu_1646_p2[0:0] === 1'b1) ? storemerge1_11_fu_1597_p3 : sel_tmp86_fu_1629_p3);

assign viterbiDecoder_state_V_load_14_fu_1735_p3 = ((sel_tmp96_fu_1729_p2[0:0] === 1'b1) ? storemerge1_12_fu_1680_p3 : sel_tmp93_fu_1712_p3);

assign viterbiDecoder_state_V_load_15_fu_1818_p3 = ((sel_tmp103_fu_1812_p2[0:0] === 1'b1) ? storemerge1_13_fu_1763_p3 : sel_tmp100_fu_1795_p3);

assign viterbiDecoder_state_V_load_1_fu_661_p3 = ((sel_tmp6_fu_655_p2[0:0] === 1'b1) ? storemerge1_fu_614_p3 : sel_tmp3_fu_638_p3);

assign viterbiDecoder_state_V_load_2_fu_739_p3 = ((sel_tmp12_fu_733_p2[0:0] === 1'b1) ? storemerge1_1_fu_684_p3 : sel_tmp7_fu_716_p3);

assign viterbiDecoder_state_V_load_3_fu_822_p3 = ((sel_tmp19_fu_816_p2[0:0] === 1'b1) ? storemerge1_2_fu_767_p3 : sel_tmp16_fu_799_p3);

assign viterbiDecoder_state_V_load_4_fu_905_p3 = ((sel_tmp26_fu_899_p2[0:0] === 1'b1) ? storemerge1_3_fu_850_p3 : sel_tmp23_fu_882_p3);

assign viterbiDecoder_state_V_load_5_fu_988_p3 = ((sel_tmp33_fu_982_p2[0:0] === 1'b1) ? storemerge1_4_fu_933_p3 : sel_tmp30_fu_965_p3);

assign viterbiDecoder_state_V_load_6_fu_1071_p3 = ((sel_tmp40_fu_1065_p2[0:0] === 1'b1) ? storemerge1_5_fu_1016_p3 : sel_tmp37_fu_1048_p3);

assign viterbiDecoder_state_V_load_7_fu_1154_p3 = ((sel_tmp47_fu_1148_p2[0:0] === 1'b1) ? storemerge1_6_fu_1099_p3 : sel_tmp44_fu_1131_p3);

assign viterbiDecoder_state_V_load_8_fu_1237_p3 = ((sel_tmp54_fu_1231_p2[0:0] === 1'b1) ? storemerge1_7_fu_1182_p3 : sel_tmp51_fu_1214_p3);

assign viterbiDecoder_state_V_load_9_fu_1320_p3 = ((sel_tmp61_fu_1314_p2[0:0] === 1'b1) ? storemerge1_8_fu_1265_p3 : sel_tmp58_fu_1297_p3);

assign viterbiDecoder_state_V_load_s_fu_583_p3 = ((tmp_25_2_reg_1887[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_2);

assign viterbiDecoder_survivorWindow_15_fu_567_p3 = ((tmp_27_3_reg_1872[0:0] === 1'b1) ? tmp_30_3_fu_561_p2 : tmp_34_3_cast_fu_557_p1);

assign viterbiDecoder_survivors_V_loa_1_fu_474_p3 = ((tmp_s_reg_1857[0:0] === 1'b1) ? tmp_8_fu_468_p2 : tmp_7_fu_460_p3);

assign viterbiDecoder_survivors_V_loa_2_fu_511_p3 = ((tmp_27_1_reg_1862[0:0] === 1'b1) ? tmp_30_1_fu_505_p2 : tmp_34_1_fu_495_p4);

assign viterbiDecoder_survivors_V_loa_3_fu_546_p3 = ((tmp_27_2_reg_1867[0:0] === 1'b1) ? tmp_30_2_fu_540_p2 : tmp_34_2_fu_530_p4);

always @ (posedge ap_clk) begin
    viterbiDecoder_distance_V_0[3:2] <= 2'b00;
    viterbiDecoder_distance_V_1[3:2] <= 2'b00;
    viterbiDecoder_distance_V_2[3:2] <= 2'b00;
    viterbiDecoder_distance_V_3[3:2] <= 2'b00;
end

endmodule //doDecode_decode