// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================

`timescale 1 ns / 1 ps

(* CORE_GENERATION_INFO="doDecode,hls_ip_2016_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7a35tcpg236-1,HLS_INPUT_CLOCK=5.500000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=14.730000,HLS_SYN_LAT=17,HLS_SYN_TPT=1,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=223,HLS_SYN_LUT=363}" *)

module doDecode (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        indat_V,
        outdat_V,
        outdat_V_ap_vld
);

parameter    ap_ST_pp0_stg0_fsm_0 = 1'b1;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [1:0] indat_V;
output  [0:0] outdat_V;
output   outdat_V_ap_vld;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg outdat_V_ap_vld;

(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
reg    ap_sig_cseq_ST_pp0_stg0_fsm_0;
reg    ap_sig_16;
wire    ap_reg_ppiten_pp0_it0;
reg    ap_reg_ppiten_pp0_it1;
reg    ap_reg_ppiten_pp0_it2;
reg    ap_reg_ppiten_pp0_it3;
reg    ap_reg_ppiten_pp0_it4;
reg    ap_reg_ppiten_pp0_it5;
reg    ap_reg_ppiten_pp0_it6;
reg    ap_reg_ppiten_pp0_it7;
reg    ap_reg_ppiten_pp0_it8;
reg    ap_reg_ppiten_pp0_it9;
reg    ap_reg_ppiten_pp0_it10;
reg    ap_reg_ppiten_pp0_it11;
reg    ap_reg_ppiten_pp0_it12;
reg    ap_reg_ppiten_pp0_it13;
reg    ap_reg_ppiten_pp0_it14;
reg    ap_reg_ppiten_pp0_it15;
reg    ap_reg_ppiten_pp0_it16;
reg    ap_reg_ppiten_pp0_it17;
reg    grp_doDecode_decode_fu_85_ap_start;
wire    grp_doDecode_decode_fu_85_ap_done;
wire    grp_doDecode_decode_fu_85_ap_idle;
wire    grp_doDecode_decode_fu_85_ap_ready;
wire   [0:0] grp_doDecode_decode_fu_85_ap_return;
reg   [0:0] ap_NS_fsm;
reg    ap_sig_grp_doDecode_decode_fu_85_ap_start;
reg    ap_sig_pprstidle_pp0;

// power-on initialization
initial begin
#0 ap_CS_fsm = 1'b1;
#0 ap_reg_ppiten_pp0_it1 = 1'b0;
#0 ap_reg_ppiten_pp0_it2 = 1'b0;
#0 ap_reg_ppiten_pp0_it3 = 1'b0;
#0 ap_reg_ppiten_pp0_it4 = 1'b0;
#0 ap_reg_ppiten_pp0_it5 = 1'b0;
#0 ap_reg_ppiten_pp0_it6 = 1'b0;
#0 ap_reg_ppiten_pp0_it7 = 1'b0;
#0 ap_reg_ppiten_pp0_it8 = 1'b0;
#0 ap_reg_ppiten_pp0_it9 = 1'b0;
#0 ap_reg_ppiten_pp0_it10 = 1'b0;
#0 ap_reg_ppiten_pp0_it11 = 1'b0;
#0 ap_reg_ppiten_pp0_it12 = 1'b0;
#0 ap_reg_ppiten_pp0_it13 = 1'b0;
#0 ap_reg_ppiten_pp0_it14 = 1'b0;
#0 ap_reg_ppiten_pp0_it15 = 1'b0;
#0 ap_reg_ppiten_pp0_it16 = 1'b0;
#0 ap_reg_ppiten_pp0_it17 = 1'b0;
end

doDecode_decode grp_doDecode_decode_fu_85(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_doDecode_decode_fu_85_ap_start),
    .ap_done(grp_doDecode_decode_fu_85_ap_done),
    .ap_idle(grp_doDecode_decode_fu_85_ap_idle),
    .ap_ready(grp_doDecode_decode_fu_85_ap_ready),
    .indat_V(indat_V),
    .ap_return(grp_doDecode_decode_fu_85_ap_return)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it1 <= 1'b0;
    end else begin
        if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
            ap_reg_ppiten_pp0_it1 <= ap_start;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it10 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it11 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it12 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it13 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it14 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it15 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it16 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it17 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it2 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it3 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it4 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it5 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it6 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it7 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it8 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it9 <= 1'b0;
    end else begin
        if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
            ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
        end
    end
end

always @ (*) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it17) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2) & (1'b0 == ap_reg_ppiten_pp0_it3) & (1'b0 == ap_reg_ppiten_pp0_it4) & (1'b0 == ap_reg_ppiten_pp0_it5) & (1'b0 == ap_reg_ppiten_pp0_it6) & (1'b0 == ap_reg_ppiten_pp0_it7) & (1'b0 == ap_reg_ppiten_pp0_it8) & (1'b0 == ap_reg_ppiten_pp0_it9) & (1'b0 == ap_reg_ppiten_pp0_it10) & (1'b0 == ap_reg_ppiten_pp0_it11) & (1'b0 == ap_reg_ppiten_pp0_it12) & (1'b0 == ap_reg_ppiten_pp0_it13) & (1'b0 == ap_reg_ppiten_pp0_it14) & (1'b0 == ap_reg_ppiten_pp0_it15) & (1'b0 == ap_reg_ppiten_pp0_it16) & (1'b0 == ap_reg_ppiten_pp0_it17))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_16) begin
        ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b1;
    end else begin
        ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~(ap_start == 1'b0))) begin
        ap_sig_grp_doDecode_decode_fu_85_ap_start = 1'b1;
    end else begin
        ap_sig_grp_doDecode_decode_fu_85_ap_start = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2) & (1'b0 == ap_reg_ppiten_pp0_it3) & (1'b0 == ap_reg_ppiten_pp0_it4) & (1'b0 == ap_reg_ppiten_pp0_it5) & (1'b0 == ap_reg_ppiten_pp0_it6) & (1'b0 == ap_reg_ppiten_pp0_it7) & (1'b0 == ap_reg_ppiten_pp0_it8) & (1'b0 == ap_reg_ppiten_pp0_it9) & (1'b0 == ap_reg_ppiten_pp0_it10) & (1'b0 == ap_reg_ppiten_pp0_it11) & (1'b0 == ap_reg_ppiten_pp0_it12) & (1'b0 == ap_reg_ppiten_pp0_it13) & (1'b0 == ap_reg_ppiten_pp0_it14) & (1'b0 == ap_reg_ppiten_pp0_it15) & (1'b0 == ap_reg_ppiten_pp0_it16))) begin
        ap_sig_pprstidle_pp0 = 1'b1;
    end else begin
        ap_sig_pprstidle_pp0 = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_grp_doDecode_decode_fu_85_ap_start)) begin
        grp_doDecode_decode_fu_85_ap_start = ap_sig_grp_doDecode_decode_fu_85_ap_start;
    end else begin
        grp_doDecode_decode_fu_85_ap_start = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_reg_ppiten_pp0_it17) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
        outdat_V_ap_vld = 1'b1;
    end else begin
        outdat_V_ap_vld = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_pp0_stg0_fsm_0 : begin
            ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_reg_ppiten_pp0_it0 = ap_start;

always @ (*) begin
    ap_sig_16 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end

assign outdat_V = grp_doDecode_decode_fu_85_ap_return;

endmodule //doDecode